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High-Performance Computing For Silicon Design

Since deployment, our HPC environment has supported a 29.87x increase in compute demand, with a 20x increase in stability. In addition, tapeout time was reduced from 25 days for the first 65nm process technology-based microprocessor in a non-HPC compute environment to 10 days for the first 45nm process technology-based microprocessor in an HPC-enabled environment. The success of the HPC environment was due to factors such as careful alignment of technology with business needs, informed risk taking, and disciplined execution. We are continuing to develop the next HPC generations to enable tapeout of successive generations of Intel processors.

Since deployment, our HPC environment has supported a 29.87x increase in compute demand, with a 20x increase in stability. In addition, tapeout time was reduced from 25 days for the first 65nm process technology-based microprocessor in a non-HPC compute environment to 10 days for the first 45nm process technology-based microprocessor in an HPC-enabled environment. The success of the HPC environment was due to factors such as careful alignment of technology with business needs, informed risk taking, and disciplined execution. We are continuing to develop the next HPC generations to enable tapeout of successive generations of Intel processors.