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  • Brand Name: Core Ultra

  • Product Number: 6526Y

  • Ordering Code: PK8072205559500

  • SPEC Code: SRN6N

  • Code Name: Emerald Rapids

Stratix® V 5SGXB6 FPGA

Specifications

Export specifications

Essentials

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40I2G

  • MM# 999Z2A
  • Spec Code SRHR9
  • Ordering Code 5SGXEB6R1F40I2G
  • Stepping A1
  • MDDS Content IDs 725986

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C2G

  • MM# 999Z2D
  • Spec Code SRHRA
  • Ordering Code 5SGXEB6R2F40C2G
  • Stepping A1
  • MDDS Content IDs 725362

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I2LG

  • MM# 999Z2F
  • Spec Code SRHRB
  • Ordering Code 5SGXEB6R2F40I2LG
  • Stepping A1
  • MDDS Content IDs 724826

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C3G

  • MM# 999Z2W
  • Spec Code SRHRN
  • Ordering Code 5SGXEB6R3F40C3G
  • Stepping A1
  • MDDS Content IDs 725435

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C2LG

  • MM# 999Z36
  • Spec Code SRHRW
  • Ordering Code 5SGXEB6R2F40C2LG
  • Stepping A1
  • MDDS Content IDs 725559

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I2G

  • MM# 999Z37
  • Spec Code SRHRX
  • Ordering Code 5SGXEB6R2F40I2G
  • Stepping A1
  • MDDS Content IDs 724796

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I3G

  • MM# 999Z38
  • Spec Code SRHRY
  • Ordering Code 5SGXEB6R2F40I3G
  • Stepping A1
  • MDDS Content IDs 725581

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I3LG

  • MM# 999Z39
  • Spec Code SRHRZ
  • Ordering Code 5SGXEB6R2F40I3LG
  • Stepping A1
  • MDDS Content IDs 725971

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C2G

  • MM# 999Z3C
  • Spec Code SRHS1
  • Ordering Code 5SGXEB6R3F40C2G
  • Stepping A1
  • MDDS Content IDs 726219

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C2LG

  • MM# 999Z3D
  • Spec Code SRHS2
  • Ordering Code 5SGXEB6R3F40C2LG
  • Stepping A1
  • MDDS Content IDs 725206

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I4G

  • MM# 999Z3F
  • Spec Code SRHS3
  • Ordering Code 5SGXEB6R3F40I4G
  • Stepping A1
  • MDDS Content IDs 725937

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C2G

  • MM# 999Z9R
  • Spec Code SRHWD
  • Ordering Code 5SGXEB6R1F40C2G
  • Stepping A1
  • MDDS Content IDs 725628

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C2LG

  • MM# 999Z9T
  • Spec Code SRHWE
  • Ordering Code 5SGXEB6R1F40C2LG
  • Stepping A1
  • MDDS Content IDs 725539

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C1G

  • MM# 999Z9Z
  • Spec Code SRHWJ
  • Ordering Code 5SGXEB6R2F40C1G
  • Stepping A1
  • MDDS Content IDs 725275

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C3G

  • MM# 999ZA0
  • Spec Code SRHWK
  • Ordering Code 5SGXEB6R2F40C3G
  • Stepping A1
  • MDDS Content IDs 724854

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40C4G

  • MM# 999ZA1
  • Spec Code SRHWL
  • Ordering Code 5SGXEB6R3F40C4G
  • Stepping A1
  • MDDS Content IDs 725158

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I3G

  • MM# 999ZA2
  • Spec Code SRHWM
  • Ordering Code 5SGXEB6R3F40I3G
  • Stepping A1
  • MDDS Content IDs 725535

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40C2LG

  • MM# 999ZF4
  • Spec Code SRHYV
  • Ordering Code 5SGXMB6R1F40C2LG
  • Stepping A1
  • MDDS Content IDs 726096

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C2LG

  • MM# 999ZF6
  • Spec Code SRHYX
  • Ordering Code 5SGXMB6R2F40C2LG
  • Stepping A1
  • MDDS Content IDs 726264

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C3G

  • MM# 999ZFG
  • Spec Code SRHZ4
  • Ordering Code 5SGXMB6R3F40C3G
  • Stepping A1
  • MDDS Content IDs 724964

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40C2G

  • MM# 999ZKD
  • Spec Code SRJ22
  • Ordering Code 5SGXMB6R1F40C2G
  • Stepping A1
  • MDDS Content IDs 725987

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I2LG

  • MM# 999ZKK
  • Spec Code SRJ27
  • Ordering Code 5SGXMB6R2F40I2LG
  • Stepping A1
  • MDDS Content IDs 725985

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C2G

  • MM# 999ZKP
  • Spec Code SRJ2B
  • Ordering Code 5SGXMB6R3F40C2G
  • Stepping A1
  • MDDS Content IDs 725020

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C1G

  • MM# 999ZKZ
  • Spec Code SRJ2G
  • Ordering Code 5SGXEB6R1F40C1G
  • Stepping A1
  • MDDS Content IDs 725385

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I3LG

  • MM# 999ZL6
  • Spec Code SRJ2P
  • Ordering Code 5SGXEB6R3F40I3LG
  • Stepping A1
  • MDDS Content IDs 726318

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40I2G

  • MM# 999ZMP
  • Spec Code SRJ3U
  • Ordering Code 5SGXMB6R1F40I2G
  • Stepping A1
  • MDDS Content IDs 725088

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40I2LG

  • MM# 999ZMR
  • Spec Code SRJ3V
  • Ordering Code 5SGXMB6R1F40I2LG
  • Stepping A1
  • MDDS Content IDs 725974

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C1G

  • MM# 999ZMW
  • Spec Code SRJ3Y
  • Ordering Code 5SGXMB6R2F40C1G
  • Stepping A1
  • MDDS Content IDs 724948

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C2G

  • MM# 999ZMX
  • Spec Code SRJ3Z
  • Ordering Code 5SGXMB6R2F40C2G
  • Stepping A1
  • MDDS Content IDs 725351

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I3LG

  • MM# 999ZMZ
  • Spec Code SRJ40
  • Ordering Code 5SGXMB6R2F40I3LG
  • Stepping A1
  • MDDS Content IDs 724857

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C2LG

  • MM# 999ZNA
  • Spec Code SRJ4A
  • Ordering Code 5SGXMB6R3F40C2LG
  • Stepping A1
  • MDDS Content IDs 724920

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C4G

  • MM# 999ZNC
  • Spec Code SRJ4B
  • Ordering Code 5SGXMB6R3F40C4G
  • Stepping A1
  • MDDS Content IDs 726271

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40I3G

  • MM# 999ZND
  • Spec Code SRJ4C
  • Ordering Code 5SGXMB6R3F40I3G
  • Stepping A1
  • MDDS Content IDs 725321

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40I3LG

  • MM# 999ZNG
  • Spec Code SRJ4D
  • Ordering Code 5SGXMB6R3F40I3LG
  • Stepping A1
  • MDDS Content IDs 726116

Stratix® V 5SGXB6 FPGA 5SGXMB6R1F40C1G

  • MM# 999ZTL
  • Spec Code SRJ6R
  • Ordering Code 5SGXMB6R1F40C1G
  • Stepping A1
  • MDDS Content IDs 725093

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C3G

  • MM# 999ZTM
  • Spec Code SRJ6S
  • Ordering Code 5SGXMB6R2F40C3G
  • Stepping A1
  • MDDS Content IDs 726067

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I2G

  • MM# 999ZTN
  • Spec Code SRJ6T
  • Ordering Code 5SGXMB6R2F40I2G
  • Stepping A1
  • MDDS Content IDs 726186

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I3G

  • MM# 999ZTP
  • Spec Code SRJ6U
  • Ordering Code 5SGXMB6R2F40I3G
  • Stepping A1
  • MDDS Content IDs 725395

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40I4G

  • MM# 999ZTX
  • Spec Code SRJ6Z
  • Ordering Code 5SGXMB6R3F40I4G
  • Stepping A1
  • MDDS Content IDs 726042

Retired and discontinued

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F43I2N

  • MM# 969088
  • Spec Code SR7MF
  • Ordering Code 5SGXEB6R1F43I2N
  • Stepping A1
  • MDDS Content IDs 697073

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40I2L

  • MM# 969089
  • Spec Code SR7MG
  • Ordering Code 5SGXEB6R2F40I2L
  • Stepping A1
  • MDDS Content IDs 697715

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F40C1N

  • MM# 969090
  • Spec Code SR7ME
  • Ordering Code 5SGXEB6R1F40C1N
  • Stepping A1
  • MDDS Content IDs 702908

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43C1N

  • MM# 969091
  • Spec Code SR7MJ
  • Ordering Code 5SGXEB6R2F43C1N
  • Stepping A1
  • MDDS Content IDs 699324

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43I2LN

  • MM# 969094
  • Spec Code SR7MM
  • Ordering Code 5SGXEB6R2F43I2LN
  • Stepping A1
  • MDDS Content IDs 695006

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F43C2LN

  • MM# 969096
  • Spec Code SR7ML
  • Ordering Code 5SGXEB6R2F43C2LN
  • Stepping A1
  • MDDS Content IDs 702328

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40I3N

  • MM# 969255
  • Spec Code SR7SC
  • Ordering Code 5SGXMB6R2F40I3N
  • Stepping A1
  • MDDS Content IDs 697503

Stratix® V 5SGXB6 FPGA 5SGXMB6R3F40C4N

  • MM# 969258
  • Spec Code SR7SF
  • Ordering Code 5SGXMB6R3F40C4N
  • Stepping A1
  • MDDS Content IDs 700473

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F43C2N

  • MM# 969364
  • Spec Code SR7VK
  • Ordering Code 5SGXMB6R2F43C2N
  • Stepping A1
  • MDDS Content IDs 692734

Stratix® V 5SGXB6 FPGA 5SGXMB6R2F40C2N

  • MM# 969365
  • Spec Code SR7VH
  • Ordering Code 5SGXMB6R2F40C2N
  • Stepping A1
  • MDDS Content IDs 693385

Stratix® V 5SGXB6 FPGA 5SGXEB6R1F43C2LN

  • MM# 970492
  • Spec Code SR8R9
  • Ordering Code 5SGXEB6R1F43C2LN
  • Stepping A1
  • MDDS Content IDs 699967

Stratix® V 5SGXB6 FPGA 5SGXEB6R2F40C2N

  • MM# 970493
  • Spec Code SR8RA
  • Ordering Code 5SGXEB6R2F40C2N
  • Stepping A1
  • MDDS Content IDs 699311

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F40I3LN

  • MM# 970496
  • Spec Code SR8RD
  • Ordering Code 5SGXEB6R3F40I3LN
  • Stepping A1
  • MDDS Content IDs 697925

Stratix® V 5SGXB6 FPGA 5SGXEB6R3F43C2LN

  • MM# 970497
  • Spec Code SR8RE
  • Ordering Code 5SGXEB6R3F43C2LN
  • Stepping A1
  • MDDS Content IDs 694731

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN Information

SRHR9

SRHRB

SRHRA

SRHYV

SRHZ4

SR8R9

SR8RE

SR8RD

SR8RA

SRHYX

SRJ4A

SRJ4B

SRJ4C

SRJ4D

SRJ3Y

SRJ3Z

SRJ3U

SRJ3V

SR7SF

SR7SC

SRJ40

SRJ6S

SRJ2P

SRJ6T

SRJ6U

SRJ6Z

SRJ2G

SR7VK

SR7VH

SRJ6R

SR7ML

SRHWE

SRHWD

SR7MJ

SRJ2B

SR7MG

SR7MF

SRHRZ

SR7ME

SRHRY

SRHWM

SRJ27

SRHWL

SRHWK

SRHWJ

SR7MM

SRHS1

SRHRN

SRJ22

SRHRX

SRHRW

SRHS3

SRHS2

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Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count†

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers†

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate†

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.

Refer to Datasheet for formal definitions of product properties and features.

‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.

“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.