Module Instance | Base Address | Register Address |
---|---|---|
i_nand_config | 0xFFB80000 | 0xFFB80100 |
Offset: 0x100
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
twhr2 RW 0x14 |
Reserved |
we_2_re RW 0x32 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
13:8 | twhr2 | Signifies the number of controller clocks that should be introduced between the last command of a random data output command to the start of the data transfer. |
RW | 0x14 |
5:0 | we_2_re | Signifies the number of bus interface clk_x clocks that should be introduced between write enable going high to read enable going low. The number of clocks is the function of device parameter Twhr and controller clock frequency. |
RW | 0x32 |