sbcfg2

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA064

Offset: 0x64

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_srf_entry_exit_block

0x0

cfg_srf_autoexit_en

0x0

cfg_user_rfsh_en

0x0

cfg_sb_cg_disable

0x0

cfg_mps_dqstrk_disable

0x0

cfg_mps_zqcal_disable

0x0

cfg_srf_zqcal_disable

0x0

sbcfg2 Fields

Bit Name Description Access Reset
7:6 cfg_srf_entry_exit_block
Blocking arbiter from issuing cmds for the 4 cases, 2
RW 0x0
5 cfg_srf_autoexit_en
Setting to 1 to enable controller to exit Self Refresh when new command is detected
RW 0x0
4 cfg_user_rfsh_en
Setting to 1 to enable user refresh
RW 0x0
3 cfg_sb_cg_disable
Set to 1 to disable mem_ck gating during self refresh and deep power down
RW 0x0
2 cfg_mps_dqstrk_disable
Set to 1 to disable DQS Tracking after Maximum Power Saving exit
RW 0x0
1 cfg_mps_zqcal_disable
Set to 1 to disable ZQ Calibration after Maximum Power Saving exit
RW 0x0
0 cfg_srf_zqcal_disable
Set to 1 to disable ZQ Calibration after self refresh
RW 0x0