This document provides information on each parameter in the Controller Settings tab.
Controller Architecture
Choose which of the two available controller architectures you wish to use. The High Performance Controller II is a completely new controller architecture that offers significantly more efficient memory access as well as increased flexibility. It offers look-ahead bank management, a more flexible Avalon interface, the option of run-time configuration and other advanced features.
The new High Performance Controller II architecture is recommended for all new designs and where possible, existing designs should also be upgraded.
Low Power Mode Parameters
Enable Self-Refresh Controls
Select this option to enable the self-refresh signals on the controller top level. These controls allow you to control when the memory is placed into self-refresh mode.
Enable Power Down Controls
Select this option to enable the power down signals on the controller top level. These controls allow you to control when the memory is placed into power down mode.
This option is not available if you have chosen the High Performance Controller II architecture.
Enable Auto Power Down
Select this option to allow the controller to automatically place the memory into power down mode after a specified number of idle cycles. The controller considers the memory to be idle if there are no user read or write requests in its command queue. You can specify the number of idle cycles after which the controller powers down the memory in the Auto Power Down Cycles box. The legal range is from 1 to 65,535 controller clock cycles. If you have enabled the Configuration and Status Register Interface, you can change the time-out value and observe whether or not the memory is currently powered down.
The Auto Power Down feature is only available when you have chosen the High Performance II Controller architecture.
Efficiency Parameters
Enable User Auto-Refresh Controls
Select this option to enable the user auto-refresh control signals on the controller top level. These control signals allow you to control when the controller issues memory auto-refresh commands. User auto-refresh requests have higher priority than read or write requests and so will be serviced as soon as possible after they are presented by the user.
Enable Auto-Precharge Control
Select this option to enable the auto-precharge control on the controller top level. Asserting the auto-precharge control signal while requesting a read or write burst allows you to specify whether or not the controller should close (auto-precharge) the currently open page at the end of the read or write burst.
If you are using the High Performance II Controller architecture and you have chosen a maximum local burst count greater than the memory burst count, the controller will only issue the auto-precharge command for the last memory command in the burst, allowing you to use this feature even with long bursts.
Local-to-Memory Address Mapping
This option allows you to control the mapping between the address bits on the Avalon interface and the chip, row, bank and column bits on the memory.
If your application issues bursts that are greater than the column size of the memory device, choose the Chip-Row-Bank-Column option. This allows the controller to use its look-ahead bank management feature to hide the effect of changing the currently open row when the burst reaches the end of the column. If, on the other hand, your application has several masters that each use separate areas of memory, choose the Chip-Bank-Row-Column option. This allows you to use the top address bits to allocate a physical bank in the memory to each master. This avoids different masters accessing the same bank which is likely to cause inefficiency as the controller must then open and close rows in the same bank.
This option is only available when you have chosen the High Performance Controller II architecture.
Command Queue Look-ahead Depth
Select a look-ahead depth value to control how many read or writes requests the look-ahead bank management logic examines. Larger numbers are likely to increase the efficiency of the bank management, but at the cost of higher resource usage. Smaller values may be less efficient, but also use fewer resources.
This option is only available when you have chosen the High Performance Controller II architecture.
Local Maximum Burst Count
Select a burst count to configure the maximum Avalon burst count that the controller slave port will accept. If all the important masters in your system issue Avalon read or write bursts, set the local maximum burst count value to the same value as your masters. If the masters in your system do not issue read or write bursts, select a maximum burst count of 1. This prevents any unnecessary burst adaption logic in the system between your masters and the memory controller slave port.
This option is only available when you have chosen the High Performance Controller II architecture.
Advanced Features
Enable Configuration and Status Register Interface
Select this option to enable run-time configuration and status of the memory controller. Enabling this option adds an additional Avalon Memory-Mapped slave port to the memory controller top level. Using this slave port, you can change or read out the memory timing parameters, memory address sizes, mode register settings and controller status. If Error Detection and Correction Logic is enabled, the same slave port also allows you to control and retrieve the status of this logic.
This option is only available when you have chosen the High Performance Controller II architecture.
Enable Error Detection and Correction Logic
Select this option to enable Error Correcting Code (ECC) for single-bit error correction and double-bit error detection. Your memory interface must be a multiple of 40 or 72 bits wide in order to be able to use ECC.
The 40-bit ECC option is only available when you have chosen the High Performance Controller II architecture.
Enable Auto Error Correction
Select this option to allow the controller to perform auto correction when a single-bit error has been detected by the ECC logic. Alternatively, you can disable auto error correction and schedule the error correction at the desired time for better system efficiency.
This option is only available when you have chosen the High Performance Controller II architecture.
Enable Multi-cast Write Control
Select this option to enable the multi-cast write control on the controller top level. Asserting the multi-cast write control when requesting a write burst will cause the write data to be written to all the chip selects in the memory system. This advanced feature is intended for systems that issue many read and write bursts to unpredictable addresses. If the same data is written to multiple locations, the probability of being able to read it back from one of those locations without having to wait for the row cycle time (tRC) increases. Multi-cast write is not supported if the ECC logic is enabled or for registered DIMM interfaces.
This option is only available when you have chosen the High Performance Controller II architecture.
Use clocks from another controller
Enable this option to allow a controller to use the Avalon clock from another controller in the system that has a compatible PLL. This allows you to create SOPC Builder systems that have two or more memory controllers that are synchronous to your master logic. If you don’t share the clocks between controllers, the resulting system will have clock crossing logic inserted and will be less efficient.
Local Interface Protocol
Altera recommends that you use the Avalon Memory-Mapped interface for all new and existing designs. Altera provides a very simple reference design to help you convert your existing design from the Native Interface to an Avalon-MM interface.
The only significant difference between the Avalon-MM and the Native Interface is the write data timing. In Avalon-MM interface mode, the user logic presents a write request, address, burst count, and the first beat of write data at the same time. The subsequent write data beats are placed into the FIFO until they are needed. In the Native interface, the user logic presents a write request, address, and burst count. The controller then requests the correct number of write data beats from the user via the write data request signal.
The High Performance Controller II architecture only supports the Avalon-MM interface.