External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families

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ID 710283
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to this Handbook 2. Recommended Design Flow 3. Selecting Your Memory 4. Selecting Your FPGA Device
1. Introduction to this Handbook x
1.1. Introduction to Memory Solutions 1.2. Protocol Support Matrix 1.3. Document Revision History
2. Recommended Design Flow x
2.1. Getting Started With External Memory Interfaces 2.2. Document Revision History
2.1. Getting Started With External Memory Interfaces x
2.1.1. Selecting Your External Memory Device 2.1.2. Selecting Your FPGA 2.1.3. Planning Your Pin Requirements 2.1.4. Planning Your FPGA Resources 2.1.5. Determining Your Board Layout 2.1.6. Specifying Parameters for Your External Memory Interface 2.1.7. Performing Functional Simulation 2.1.8. Adding Design Constraints 2.1.9. Compiling Your Design and Verifying Timing 2.1.10. Verifying and Debugging External Memory Interface Operation
3. Selecting Your Memory x
3.1. DDR SDRAM Features 3.2. DDR2 SDRAM Features 3.3. DDR3 SDRAM Features 3.4. QDR, QDR II, and QDR II+ SRAM Features 3.5. RLDRAM II and RLDRAM 3 Features 3.6. LPDDR2 Features 3.7. Memory Selection 3.8. Example of High-Speed Memory in Embedded Processor 3.9. Example of High-Speed Memory in Telecom 3.10. Document Revision History
4. Selecting Your FPGA Device x
4.1. Memory Standards 4.2. I/O Interfaces 4.3. Wraparound Interfaces 4.4. Read and Write Leveling 4.5. Dynamic OCT 4.6. Device Settings Selection 4.7. Document Revision History
4.6. Device Settings Selection x
4.6.1. Device Speed Grade 4.6.2. Device Operating Temperature 4.6.3. Device Package Size 4.6.4. Device Density and I/O Pin Counts
1. Introduction to this Handbook
2. Recommended Design Flow
3. Selecting Your Memory
4. Selecting Your FPGA Device

1.1. Introduction to Memory Solutions

Intel® FPGAs achieve optimal memory interface performance with external memory IP. Intel provides the fastest, most efficient, and lowest latency memory interface IP cores, designed to easily interface with today's higher speed memory devices.

Intel® supports a wide variety of memory interfaces suitable for applications ranging from routers and switches to video cameras. You can easily implement Intel® ’s intellectual property (IP) using the memory IP core functions through the Intel® Quartus® Prime software. The Intel® Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA device.

Refer to the External Memory Interface Spec Estimator page for the maximum speeds supported by Intel® FPGAs.

The external memory interface IP provides the following components:
  • Physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
  • Memory controller which implements all the memory commands and protocol-level requirements.
  • Multi-port front end (MPFE) which allows multiple components inside the FPGA device to share a common memory interface. The MPFE is available in Arria® V and Cyclone® V devices.
Figure 1. Memory Interface Architecture


Intel® 's FPGAs provide two types of memory solutions, depending on device family: soft memory IP and hard memory IP. The soft memory IP gives you the flexibility to design your own interfaces to meet your system requirements and still benefit from the industry leading performance. The hard memory IP is designed to give you a complete out-of-the-box experience when designing a memory controller.

The following table lists features of the soft and hard memory IP.

Table 1.  Features of the Soft and Hard Memory IP

Soft Memory IP

Hard Memory IP

  • Includes hardened PHY with soft controller.
  • Allows maximum flexibility in choosing location, size, and configuration of the memory interface.
  • Can optionally be used in PHY-only mode to integrate with a custom user-designed controller.
  • Includes hardened PHY, hardened controller, and hardened MPFE.
  • Supports maximum performance and lowest latency.
  • May have a fixed location on a device and/or a fixed pinout for address and command signals.
  • Simplifies the overall integration of a memory interface and provides an out-of-the-box experience for every designer.

Intel® provides modular memory solutions that allow you to customize your memory interface design to a variety of configurations:

  • PHY with your own controller
  • PHY with Intel® controller
  • PHY with Intel® controller and a multiport front end. (MPFE is a configurable block available for hard interfaces in Arria V and Cyclone V devices.)

You can also build a custom PHY, a custom controller, or both, as desired.

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