Digital Signal Processing
Variable-precision DSP architecture with hardened floating-point operators integrated into Generation 10 FPGAs and SoCs
Intel offers exclusive hard floating-point solutions. The revolutionized hardened DSP blocks are industry’s first with native support for IEEE 754 single-precision floating point in dedicated hardened circuitry. This technological breakthrough allows the variable-precision DSP blocks to be configured at compile time into the IEEE 754 floating-point, standard-precision (18 bit), or high-precision (27 bit) mode.
In floating-point mode, each DSP block provides a single-precision multiplier and single-precision adder enabling DSP designers with the following key benefits:
Three DSP block modes available in Intel® Arria® 10 and Intel® Stratix® 10 FPGAs and SoCs
DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that allows push button Hardware Description Language (HDL) generation of DSP algorithms directly from MathWorks* Simulink* environment. DSP Builder for Intel® FPGAs adds additional Intel libraries alongside existing Simulink* libraries with the Intel® DSP Builder Advanced Blockset and DSP Builder Standard Blockset. Check out the latest tool capabilities and detailed features by visiting the DSP Builder for Intel® FPGAs page.
Intel’s intellectual property (IP) portfolio includes a unique combination of DSP IP cores and Forward Error Detection and Correction IP cores that complement DSP Builder for Intel® FPGAs Advanced Blockset Design Examples. Find the right DSP IP for your designs here.