Intel® Arria® 10 FPGA – 12G-SDI Audio Reference Design

Intel® Arria® 10 FPGA – 12G-SDI Audio Reference Design

714341
9/9/2020

Introduction

The Intel® Arria® 10 FPGA 12G-SDI Audio Embed/Extract Reference Design provides an application example for embedding and de-embedding of digital audio data into a 12G-SDI video signal.

Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

20.1

IP Cores (32)
IP Core IP Core Category
ALTCLKCTRL ClocksPLLsResets
Altera IOPLL ClocksPLLsResets
Arria 10 FPLL ClocksPLLsResets
Reset Controller QsysInterconnect
Avalon-MM Clock Crossing Bridge QsysInterconnect
Avalon-ST Dual Clock FIFO QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Memory-Mapped Router QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
altera_jtag_avalon_master QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Arria 10 Transceiver Native PHY TransceiverPHY
Transceiver PHY Reset Controller TransceiverPHY
SDI II TransceiverPHY
FIFO OnChipMemory
Audio Embed Audio & Video
Audio Extract Audio & Video
Top level generated instrumentation fabric Debug & Performance
Altera Arria 10 XCVR Reset Sequencer Other

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 20.1.0 Pro


Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

20.1