Browse through the development tools available for building software and creating FPGA designs for Intel® SoC FPGAs.
The Intel® Quartus® Prime Software provides everything you need to design with Intel® SoC FPGAs. It is a complete development package that comes with a user-friendly GUI and technology to help you bring your ideas into reality. The Intel® Quartus® Prime Software environment includes a host of tools and features to enhance productivity, many of which are the first in the industry.
The Intel® SoC FPGA Embedded Development Suite (SoC EDS) is a comprehensive tool suite for embedded software development for Intel® SoC FPGAs. It contains development tools, utility programs, run-time software, and application examples to expedite firmware and application software for SoC FPGA embedded systems. With SoC EDS, you get all the tools you need to work more productively, improve your software quality, and ultimately get to market faster.
Every SoC FPGA-based embedded system design is unique due to the customized logic programmed into the FPGA. To perform system debugging effectively, the ARM* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition toolkit dynamically adapts to your configuration. It unifies all software debugging information from the CPU and FPGA domains and presents them in an organized fashion within the standard DS-5 user interface. Intel and ARM developed the toolkit to give you an unprecedented level of FPGA-visibility and control that delivers substantial productivity gains.
The Intel® FPGA SDK for Open Computing Language (OpenCL™) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher-level software development flow. Emulate your OpenCL™ C accelerator code on an x86-based host in seconds by getting a detailed optimization report with specific algorithm pipeline dependency information. You can also prototype the accelerator kernel on a virtual FPGA fabric in minutes and push the longer compile time to the end when you are pleased with your kernel code results.
Intel, in collaboration with Mentor Graphics*, provides embedded software developers access to virtual platforms. These platforms support Intel’s entire SoC FPGA portfolio, including the Intel® Arria® 10 SoC, the industry’s only 20 nm SoC FPGA, and the third generation 14nm Intel® Stratix® 10 SoCs with a 64-bit quad-core ARM* Cortex*-A53 processor. The virtual platforms, built with Mentor Graphics* Vista tools, are prebuilt, fully functional simulations models of the SOC FPGAs ARM* processor subsystems.
The SoC FPGA virtual platforms includes an instruction set simulator CPU model plus peripheral device models, delivered as a standalone binary executable. You Download, install, and run the executable with a prebuilt Linux* image on a host PC…. You can use any GDB-compatible debug environment, including ARM* Development Studio 5 Intel® FPGA Edition toolkit for comprehensive debugging of bare metal, Linux* and other OS applications.
Basing the SoC FPGA virtual platform on the Mentor Graphics* Vista tool suite provides users a seamless migration to Mentor Graphics’ Vista Virtual Prototyping solutions. The Vista Virtual Prototyping tool suite provides additional insight into hardware/software interaction or non-intrusive profiling and analysis. It also extends the SoC FPGA virtual platform, including timing-approximate or timing-accurate CPU models.
Software developers can use the Intel® Stratix® 10 SoC virtual platform to start embedded software development and debug for the integrated quad-core ARM* Cortex*-A53 processor subsystem well before first silicon availability. Additionally, SoC FPGA virtual platforms simplify embedded software development and reduce the need for expensive hardware by enabling large development teams to perform application development and software regression testing in a virtual environment modeling an Intel® SoC FPGA.
For more information on the Intel® SoC FPGA virtual platform, refer to the following links:
To download the latest documentation for the Intel® Arria® 10 SoC Virtual Platform, refer to the following link:
To download the latest documentation for the Intel® Stratix® 10 SoC Virtual Platform, refer to the following link:
For support questions regarding the SoC FPGA virtual platform go to the Forums page on Rocketboards.org:
Intel contributes to the Linux community to enable our SoC FPGA and Nios® II processor customers via the community portal RocketBoards.org. We ensure the availability of Linux* kernels, U-boot, and the meta-Intel layers for Angstrom and the Yocto Project for the Intel® SoC FPGAs. Intel contributes to the open-source community to enable the Linux* kernel to run on its SoC FPGA and Nios® II processor architectures. Contributions include improvements to the general kernel as well as new SoC FPGA and Nios® II processor-specific functions, such as the FPGA manager framework. By nature, these improvements benefit everyone in the Linux* community.
Intel keeps up with the Linux community by upgrading to the latest stable kernel on kernel.org. Additionally, Intel supports a modern release strategy by updating public git trees every two weeks on RocketBoards.org.
Intel's approach to Linux for SoC FPGAs and the Nios® II processor is centered on upstreaming fixes and improvements of the SoC FPGA and Nios II processor code primarily to kernel.org and DENX.de. Consequently, Intel assembled a Linux team with upstreaming as a key strategy.
In addition to providing the latest stable kernel for the SoC FPGA architecture, Intel also supports U-Boot, LTSI kernel with and without PREEMPT_RT, and a meta-Intel layer. This code runs (and was tested on) the Yocto-compatible, Angstrom distribution. You can obtain the code via the public code repositories on RocketBoards.org, which is a “one-stop-shop” for Linux developers working on Intel® SoC FPGAs.
RocketBoards.org code repositories include:
Intel contributes to the Linux kernel, kernel.org. Specifically, Intel innovates by augmenting the Linux kernel with new features, such as an FPGA manager framework for programming and reconfiguring the FPGA. Furthermore, Intel is enhancing the kernel to better handle memory map reconfiguration via dynamic device trees.
OpenCL™ and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.