Marketing Status
Launched
Launch Date
2013
Lithography
14 nm

Resources

Logic Elements (LE)
841000
Adaptive Logic Modules (ALM)
284960
Adaptive Logic Module (ALM) Registers
1139840
Fabric and I/O Phase-Locked Loops (PLLs)
16
Maximum Embedded Memory
72 Mb
Digital Signal Processing (DSP) Blocks
2016
Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
Hard Processor System (HPS)
Quad-core 64-bit ARM* Cortex*-A53
Hard Memory Controllers
Yes
External Memory Interfaces (EMIF)
DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys

I/O Specifications

Maximum User I/O Count
688
I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
Maximum LVDS Pairs
336
Maximum Non-Return to Zero (NRZ) Transceivers
48
Maximum Non-Return to Zero (NRZ) Data Rate
28.3 Gbps
Transceiver Protocol Hard IP
PCIe Gen3, 100G Ethernet

Advanced Technologies

Hyper-Registers
Yes
FPGA Bitstream Security
Yes

Package Specifications

Package Options
F1760

Supplemental Information