AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Public
Document Table of Contents

1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

This reference design demonstrates the implementation of two x8-lane JESD204B (Duplex) IP cores synchronization in Intel® Arria® 10 device through FMC loopback card. This is done by emulating the interface between one converter card with two x8-lane JESD204B (Duplex) IP cores. The transmitters of the IP cores are emulated to have two analog-to-digital converters (ADC) to form 16 lanes. The serial data from the TX of the IP cores are loopback to the RX through FMC loopback card. Additionally, the design allows internal serial loopback mode for debugging purpose.

The following are the parameters used for the reference design.

  • LMF=841
  • S=1
  • K=32
  • Scrambler enabled
  • Data rate of the transceiver lanes is 6.0 Gbps in bonding mode (TX)