Verilog HDL: Signed Multiplier with Registered I/O

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This example describes an 8-bit signed multiplier with registered I/O in Verilog HDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.

Figure 1. Signed multiplier top-level diagram.

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Table 1. Signed Multiplier Port Listing

Port Name

Type

Description

a[7:0],
b[7:0]

Input

8-bit signed registered data inputs to multiplier unit. Input data is fed to the multiplier on each clock cycle.

clk

Input

Clock.

out[15:0]

Output

16-bit signed output of multiplier unit.
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