Article ID: 000073983 Content Type: Troubleshooting Last Reviewed: 12/18/2020

Why does the Intel® Programmable Acceleration Card N3000 when receiving Ethernet pause frames on one port pause transmission on all ports?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to an RTL coding error in the supplied Intel® PAC N3000 RTL code, when one port receives a pause frame, all ports pause transmission.  The expected operation is for only the port receiving the pause frame to pause transmission.

    Resolution

    To work around this RTL coding error, modify SystemVerilog file n3000_1_3_v1.5.7/Factory/hw/pac/eth_wrapper/rtl/eth_demux_logic.sv

    From:

    always_ff @(posedge clk or posedge rst) begin

            if (rst) begin

           
                i_avst.ready <= '0;

            end

            else begin

           
                i_avst.ready <= &wire_ready;

            end

    end

     

    Corrected:

    always_comb begin

           
        case({rg_i_avst_valid,rg_i_avst_channel})

               
            100 : wire_ready_o = wire_ready[0];

               
            101 : wire_ready_o = wire_ready[1];

               
            110 : wire_ready_o = wire_ready[2];

               
            111 : wire_ready_o = wire_ready[3];

               
            default : wire_ready_o = 1'b1 ;

           
        endcase

    end

       

    always_ff @(posedge clk or posedge rst) begin

            if (rst) begin

           
                i_avst.ready <= '0;

            end

            else begin

           
                //i_avst.ready <= &wire_ready;

           
                i_avst.ready <= wire_ready_o;

            end

    end

     Save the edited file and re-build N3000 FPGA image.  

    This coding error is planned to be fixed in a future N3000 software release.

     

    Related Products

    This article applies to 2 products

    Intel® FPGA PAC N3000
    Intel® Arria® 10 GT FPGA