Article ID: 000074004 Content Type: Troubleshooting Last Reviewed: 08/18/2023

Why is flashsm_reset reported as an unconstrained clock in the PFL IP?

Environment

  • Intel® Quartus® Prime Standard Edition
  • MicroBlaster™ Fast Passive Parallel Software Driver
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    Description

    Due to a limitation in the Intel® Quartus® Prime software, you may see flashsm_reset reported as an unconstrained clock. This occurs when you instantiate the Parallel Flash Loader (PFL) IP in an Intel® MAX® 10 device.

     

     

     

    Resolution

    flashsm_reset is not a clock, so it is safe to ignore this warning.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs