Article ID: 000074014 Content Type: Troubleshooting Last Reviewed: 11/02/2016

Why is the clock phase incorrect in my MAX 10 PLL output?

Environment

  • Intel® Quartus® Prime Standard Edition
  • PLL Intel® FPGA IP
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    Description

    Due to a problem in the Quartus® Prime Standard edition software version 16.0, the Max® 10 ALTPLL IP with phase shift setting will show an incorrect value in the TimeQuest Timing Analyzer clock report.

    Resolution

    This problem has been fixed in the Quartus Prime Standard edition software version 16.0 Update 2. 

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs