Article ID: 000074176 Content Type: Error Messages Last Reviewed: 04/21/2021

Error(18515): Attempted to route one dedicated refclk pin, xxx, to IOPLLs. In order to feed x IOPLLs, this signal must be promoted to a global clock.

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This error may be seen in the Intel® Quartus® Prime Pro Edition software version 17.1 and later when multiple IOPLLs are driven directly by one dedicated reference clock in Intel® Stratix® 10 devices.

    Resolution

    To avoid this error, promote the reference clock to a global clock with the folloing constraint in Quartus Settings File (.qsf).

    set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to xxx

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs