Article ID: 000074536 Content Type: Troubleshooting Last Reviewed: 05/10/2017

Why do I see the fitter error "Can't place multiple pins assigned to pin location PIN" for AVSTx8 data signal?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to Avalon-ST x8 mode uses the SDM_IO bank, which is dedicated IO for configuration signal, AVSTx8 cannot place to userI/O pins. 

    In Intel Stratix10® pin connection guide page7, table3. Avalon-ST x8 mode uses the SDM_IO pins. SDM IO bank is dedicated IO for configuration signal, cannot locate user I/O.

    /content/dam/altera-www/global/en_US/pdfs/literature/dp/stratix-10/pcg-01020.pdf

    In Stratix10 Configuraition User Guide page12, table4, it said AVSTx8 signals are dedicated, cannot use dual purpose user IO.

    /content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-10/ug-s10-config.pdf

    Only dual purpose configuration pins can user as user I/O during user mode. It describes in note15. AVST_DATA, AVST_VALID, and AVST_CLK.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs