Article ID: 000074905 Content Type: Troubleshooting Last Reviewed: 02/27/2018

Using BluePrint's Autoplace All feature to place the periphery generates assignments that might cause an internal error in quartus_syn

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you invoke BluePrint\'s Autoplace All feature to place the periphery for the following designs, BluePrint generates assignments that might cause an internal error in Spectra-Q Synthesis (quartus_syn) when they are added to the Quartus® Prime Settings File (.qsf):

    • Designs that have the SignalTap II Logic Analyzer Trigger in to pin feature or the Trigger out to pin feature, or both, enabled.
    • Designs that contain the Arria® 10 Transceiver Native PHY IP core with the tx_analog_reset or rx_analog_reset signal connected to the top-level inputs.
    Resolution

    If your designs satisfy the listed criteria, avoid using BluePrint\'s AutoPlace All feature. Alternatively, remove the assignments that cause the internal error in quartus_syn. These assignments have targets to hierarchy paths of the form auto_fab_0|debug.export.*. For example:

    set_location_assignment IOOBUF_X142_Y44_N18 -to auto_fab_0|debug.export.alt_sld_fab_0_splitter_receive_1[0]~output -tag "BluePrint Location Assignment"

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs