When implementing transceiver x4 bonded protocols such as XAUI or PCIe x4, there are some transceiver pin location constraint guidelines that should be followed.
The following example assumes a Stratix® II GX EP2SGX130GF1508 device but the same rule applies to all devices within the Stratix II GX family.
The physical lane ordering of the individual transceivers in each bank is numbered as follows:
Bank Lane Rx Tx
Bank 13 Lane 1 GXB_Rx1 GXB_Tx1
Bank 13 Lane 0 GXB_Rx0 GXB_Tx0
Bank 13 Lane 2 GXB_Rx2 GXB_Tx2
Bank 13 Lane 3 GXB_Rx3 GXB_Tx3
Bank 14 Lane 1 GXB_Rx5 GXB_Tx5
Bank 14 Lane 0 GXB_Rx4 GXB_Tx4
Bank 14 Lane 2 GXB_Rx6 GXB_Tx6
Bank 14 Lane 3 GXB_Rx7 GXB_Tx7
And so on for banks 15, 16, & 17.
In order to allow Quartus® II software to fit a bonded x4 protocol, the high-speed transceiver signal names must map to the relative physical transceiver channel number within a transceiver block as shown below.
Bank Lane Rx Tx
Bank 13 Lane 1 RxDatain(1) (GXB_Rx1) TxDataout(1) (GXB_Tx1)
Bank 13 Lane 0 RxDatain(0) (GXB_Rx0) TxDataout(0) (GXB_Tx0)
Bank 13 Lane 2 RxDatain(2) (GXB_Rx2) TxDataout(2) (GXB_Tx2)
Bank 13 Lane 3 RxDatain(3) (GXB_Rx3) TxDataout(3) (GXB_Tx3)
Or if you were using bank 14
Bank Lane Rx Tx
Bank 14 Lane 1 RxDatain(1) (GXB_Rx5) TxDataout(1) (GXB_Tx5)
Bank 14 Lane 0 RxDatain(0) (GXB_Rx4) TxDataout(0) (GXB_Tx4)
Bank 14 Lane 2 RxDatain(2) (GXB_Rx6) TxDataout(2) (GXB_Tx6)
Bank 14 Lane 3 RxDatain(3) (GXB_Rx7) TxDataout(3) (GXB_Tx7)
And so on for banks 15, 16, & 17.
Failure to follow these guidelines may result in a no fit or non-functional interface.