Article ID: 000075347 Content Type: Error Messages Last Reviewed: 03/15/2023

Error (15065): Clock input port inclk[0] of PLL "lvds_tx_pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error when implementing the MAX® 10 Soft TX LVDS IP in External PLL mode, using Quartus® II software version 14.1 and later. The tx_inclock is missing from the RTL source file.

    Resolution

    To work around this problem, change the Altera Soft LVDS TX IP to internal PLL mode or enable the "Register \'tx_in\' input port" option on the Transmitter Settings tab of the MAX® 10 Soft TX LVDS MegaWizard™ Plug-In Manager.

    This problem is scheduled to be fixed in a future version of the Quartus® II software.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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