Article ID: 000075597 Content Type: Troubleshooting Last Reviewed: 03/21/2022

Why does the Intel® L-/H-Tile Avalon® Streaming IP for PCI Express* report timing violations on clock domain crossing paths?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3 to 21.2, you may see timing violations between paths that are crossing clock domains in the Intel® L-/H-Tile Avalon® Streaming IP for PCI Express*.

    The Intel® L-/H-Tile Avalon® Streaming IP for PCI Express* generates the required synchronization logic for the clock domain crossing, however, the Synopsys* Design Constraints Files (.sdc) does not correctly constrain these paths.

    Resolution

    To work around this problem, follow the next steps:

    1. Download altera_pcie_s10_gen3x16_cdc Synopsys* Design Constraints file (.sdc)
    2. Add altera_pcie_s10_gen3x16_cdc.sdc to your Intel® Quartus® project
    3. altera_pcie_s10_gen3x16_cdc.sdc should be placed after the Intel® L-/H-Tile Avalon® Streaming IP for PCI Express* configuration file (.ip)

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA