Article ID: 000075744 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I not see DQS tracking signals when I implement UniPHY based DDR3 SDRAM Controller above 533MHz?

Environment

  • Quartus® II Subscription Edition
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    Description

    In Quartus® II software version 11.1SP2 and earlier, the DDR3 SDRAM UniPHY based controller IP turned on the DQS tracking feature at speeds above 533MHz so the signals afi_ctl_refresh_done, afi_seq_busy, and afi_ctl_long_idle for the DQS tracking were present in the IP.

    In Quartus II software version 12.0, upon further analysis it has been determined that DQS tracking is not needed in Stratix® V devices at any supported frequencies so the feature has been disabled.

    Resolution

    Regenerate the DDR3 SDRAM UniPHY based controller in Quartus II software 12.0 to get the most updated version of the IP.

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA