VHDL Simulation of Arria 10 EMIF IP with Riviera-PRO May Fail to Progress Under Some Circumstances

This problem affects all supported external memory protocols on Arria 10 devices. If your design uses a VHDL simulation model with an Altera EMIF bus functional model, simulation with a version of Riviera-PRO earlier than 2015.06 may fail to progress.

The workarounds for this issue are as follows:

• Simulate using Verilog instead of VHDL. This problem occurs only with VHDL.
• Use a different simulator, other than Riviera-PRO. This problem occurs only with Riviera-PRO.

This problem will be fixed in a future version.