Article ID: 000076756 Content Type: Product Information & Documentation Last Reviewed: 02/22/2019

How can the buffer size of the Intel® Arria® 10 External Memory Interface (EMIF)  IP be controlled to reduce the RAM blocks usage in the FPGA device?

Environment

  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Intel® Quartus® Prime software, the buffer size of the Platform Designer interconnect depends on two factors:

    1.     Maximum pending read transactions from an Avalon slave IP (for instance: Intel Arria® 10 EMIF IP)

    2.     Burstcount width of the Avalon MM interface

    However, the maximum pending read transactions of the EMIF IP can't be changed and is set to a fixed value of 64 to maximize the EMIF efficiency. 

    Resolution

    To work around this problem, reduce the burstcount width of the Avalon MM slave interface to reduce the buffer size of the Intel® Arria® 10 EMIF IP.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs