Article ID: 000076807 Content Type: Troubleshooting Last Reviewed: 05/10/2013

offset_cancellation_reset Signal is Not Synchronized to reconfig_clk in IP Compiler for PCI Express Stratix IV Chaining DMA Example Design

Environment

  • Quartus® II Subscription Edition
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    Description

    The offset_cancellation_reset signal in the Stratix IV chaining DMA example design for the IP Compiler for PCI Express is synchronized to changes in the reconfig_clk_locked signal and not to the reconfig_clk clock. As a result, the SERDES might occasionally function incorrectly.

    Resolution

    This issue has no workaround.

    This issue will be fixed in a future version of the IP Compiler for PCI Express chaining DMA example.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs