Article ID: 000077025 Content Type: Troubleshooting Last Reviewed: 08/15/2023

When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants does the Timing Analyzer report o_sclk signal as an unconstrained clock?

Environment

  • Intel® Quartus® Prime Pro Edition
  • E-tile Hard IP for Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants , the o_sclk signal is an asynchronous pulse routed through clock network. Timing Analyzer incorrectly identifies the o_sclk signal as a clock source and reports it as an unconstrained clock.

    Resolution

    No workaround is required, you can safely ignore this Timing Analyzer analysis of o_sclk as an unconstrained clock.

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 DX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series