Article ID: 000077401 Content Type: Troubleshooting Last Reviewed: 05/29/2019

Why do I see discontinuities in the eye diagram created using the On-Die Instrumentation (ODI) feature for Intel® Stratix® 10 L-Tile and H-Tile device transceivers?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a known silicon limitation in the On-Die Instrumentation (ODI) for the Intel® Stratix® 10 L-Tile and H-Tile devices, the ODI plotted transceiver eye may have discontinuities at horizontal phase steps 0, 32, 64 or 96 because the horizontal phase step sizes are not even in size.  As a result, the vertical eye opening may not be smooth at those steps.

    Discontinuities may be seen both when using the Transceiver Toolkit GUI to draw a transceiver eye, or when plotting the eye using Avalon Memory Mapped register transactions.

    This problem with the ODI does not affect data reception or bit error rate.

    Resolution

    This problem will not be fixed in the Intel Stratix 10 L-Tile or H-Tile devices.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA