Article ID: 000077586 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any problems with timing analysis for Stratix and Stratix GX designs implemented prior to Quartus II software version 4.1?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes; timing analysis should be rerun for Stratix® and Stratix GX designs implemented prior to the Quartus® II software version 4.1. The tco values reported by the Quartus II software version 4.0 and earlier are inaccurate. The tco changes for I/O standards with high-current drive-strength settings will be affected less than I/O standards with low current drive-strength settings.

Rerun timing analysis on designs implemented prior to the Quartus II software version 4.1 to identify any I/O timing issues. If I/O timing constraints are not met, refer to the white paper Improving Pin-to-Pin Timing in Stratix & Stratix GX Devices (PDF) for design solutions.

This problem has been fixed beginning with the Quartus II software version 4.1 and it does not affect any other devices. 

Related Products

This article applies to 2 products

Stratix® FPGAs
Stratix® GX FPGA