Article ID: 000077691 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How many additional DCLK cycles are needed to enter initialization mode in Stratix - series devices?

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Description

To enter initialization mode in Stratix® - series devices, two additional falling edges are needed on DCLK after CONF_DONE goes high. This is required whether you use the user clock (CLKUSR) or the internal initialization clock.

 

 

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Stratix® III FPGAs