Article ID: 000077775 Content Type: Product Information & Documentation Last Reviewed: 01/01/2015

How do I interface with 3.3V I/O standards in Quartus II software for Stratix IV devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Stratix® IV device family is compliant with 3.3V LVTTL and 3.3V LVCMOS I/O standards when using a VCCIO of 3.0V.  Stratix IV devices do not support VCCIO voltages of 3.3V. 

    In the Quartus® II software, you should select "3.3-V LVTTL" or "3.3-V LVCMOS" as the I/O standard in the Assignment Editor or Pin Planner.  When you compile your design, the .pin file will indicate the appropriate VCCIO voltage for the I/O banks supporting these standards.  When 3.3V LVTTL or 3.3V LVCMOS output or bidirectional pins exist in the I/O bank, the VCCIO will need to be connected to 3.0V on the PCB.

    More information can be found in I/O Features in Stratix IV Devices (PDF) and the Stratix IV GX Device Family Pin Connection Guidelines (PDF).

    Related Products

    This article applies to 3 products

    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® IV E FPGA