Article ID: 000077902 Content Type: Error Messages Last Reviewed: 04/18/2023

Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_bank.cpp, Line: 2379 m_single_ended_iostd_drive_strength >= 0

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 15.0 and earlier, you may see this internal error if you change the JTAG pin assignment from the default value.

    In MAX® 10 devices, JTAG pins are dual-purpose pins. If you use the JTAG pin as a dedicated pin, you do not need to do any pin assignment for the pin. You may get this internal error if you edit the pin assignment to anything other than the default value.

    Resolution

    To avoid the error, perform one of the following steps:

    • Revert back all JTAG pin I/O standard to the default IO standard in the pin planner.
    • Change to the default I/O standard to 3.3-V LVCMOS
    • Go to Assignments -> Device -> Device and Pin Options -> Voltage -> change "Default I/O standard" to 3.3-V LVCMOS

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs