Article ID: 000077985 Content Type: Troubleshooting Last Reviewed: 01/01/2015

The 13.0 Quartus II software release issues a warning message for Cyclone V I/O pad placement

Environment

  • Quartus® II Subscription Edition
  • I O
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The 13.0 Quartus® II software release does not include the following two I/O restriction rules for the Cyclone® V device:

    • The single-ended I/O to true differential I/O placement restriction
    • Single-ended/SSTL I/O utilization restriction for banks with true differential I/O
    Resolution

    This issue is fixed in the 13.0 Quartus II software release service pack 1 and all subsequent releases of the Quartus II software.

    If using the 13.0 Quartus II software release, when the I/O bank containing true differential I/O pins uses LVTTL, LVCMOS, or non-terminated SSTL or HSTL pins, refer to the Cyclone V Device Family Pin Connection Guidelines for single-ended output pin drive strength limitations. Contact mySupport for additional pin location requirements.

    No workaround is required when:

    • The I/O bank containing true differential I/O pins does not have single-ended LVTTL or LVCMOS pins, or
    • The I/O bank containing true differential I/O pins has terminated SSTL or HSTL I/O pins, and termination can occur on or off chip.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs