Article ID: 000078388 Content Type: Troubleshooting Last Reviewed: 01/21/2013

Why does my HPS design fail Analysis & Synthesis but report zero errors?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus II software version 12.1, you may see Analysis & Synthesis fail by report zero errors if you have not connected your Hard Processor System (HPS) directly to FPGA pins. HPS I/O must be connected to pins without any intervening logic.
    Resolution

    To work around this problem, make sure the HPS I/O are connected directly to FPGA pins.

    Future releases of the Quartus II software will give an error message for this incorrect connection.

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
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    Cyclone® V SX SoC FPGA
    Arria® V SX SoC FPGA