You may see error message below during compilation with the Quartus® II software, if your PLL mode is in Normal and Source Synchronous compensation feedback mode which requires a GCLK or RCLK feedback path to achieve the required phase relationship. If you have insufficient GCLK or RCLK resources, you may be unable to implement the compensation mode for all PLLs in your design.
Error (175001): Could not place fractional PLL<BR> Info (175028): The fractional PLL name: <PLL instance name>|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL<BR> Error (12349): The Fitter was unable to route the far global PLL feedback path for the fractional PLL. Please review the detailed help for this message for possible workarounds
To work around the issue, either move the PLL to a different location where there are sufficient GCLK or RCLK resources or change your PLL compensation mode to Direct compensation mode. Refer to the appropriate device handbook for a description of PLL compensation modes.