Article ID: 000078578 Content Type: Troubleshooting Last Reviewed: 12/31/2013

Will the receiver side of a transceiver channel be available during ATX PLL calibration of Stratix V GX/GT and Arria V GZ devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

During initial ATX PLL calibration immediately after configuration of Stratix® V GX/GT and Arria® V GZ devices, the receiver will not be available. Subsequent ATX PLL calibration processes initiated by the user will not affect the receiver data path.

Related Products

This article applies to 4 products

Arria® V GZ FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA