Article ID: 000078872 Content Type: Troubleshooting Last Reviewed: 11/02/2015

Does IP Compiler for PCIe support automatic Compliance mode detection during Compliance Base Board (CBB) testing?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No.

During CBB testing user just need to set test_in[32]=1,test_in[6]=0 and cycle through the PCIe® Gen1 and Gen2 mode using test_in[5] bit. Example design that shows how to implement CBB testing can be obtained from the PCIe Chaining DMA example design and using altpcierd_complaince_test.v(hd) module.

The testin[5] port should be asserted for a minimum of 16ns and less than 24ms and this requirement is implemented through altpcierd_complaince_test.v(hd) module.

During normal operation, user need to set test_in[32]=0, test_in[5]=1 and test_in[6]=0.

Resolution

Updates as follows:

No, IP Compiler for PCIe does not support automatic Compliance mode detection.

For Gen1 CBB testing, the user needs to set test_in[32]=1 and test_in[6]=0.
For Gen2 CBB testing, the user needs to set test_in[32]=1, test_in[6]=0 and use test_in[5] to cycle through the PCIe Gen1 and Gen2 compliance patterns.


The PCIe Chaining DMA example design contains a module which shows how to implement logic for CBB testing.  This module is named altpcierd_compliance_test.v(hd).

The test_in[5] port should be asserted for a minimum of 16ns and less than 24ms and this requirement is implemented through altpcierd_complaince_test.v(hd) module.

During normal operation, user needs to set test_in[32]=0, test_in[5]=1 and test_in[6]=0.

Related Products

This article applies to 1 products

Stratix® IV GX FPGA