Article ID: 000079214 Content Type: Troubleshooting Last Reviewed: 11/23/2011

Stratix V QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY Memory Interfaces May Exhibit Write Timing Failure

Environment

  • Quartus® II Subscription Edition
  • Nios® II Processor
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Memory interfaces targeting Stratix V devices may exhibit write setup or write hold timing failures.

    Resolution

    A workaround for interfaces running at 400MHz or slower is to enable the high-performance Nios II-based sequencer instead of the RTL-based sequencer.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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