Article ID: 000079680 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why do the tx_path_delay_10g_data and tx_path_delay_1g_data signal descriptions refer to a data width of 16/22 for the Arria® V and Stratix® V  devices in the Low Latency Ethernet 10G MAC User Guide?

Environment

  • Quartus® II Subscription Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a mistake in Table 5-16: IEEE 1588v2 Egress Transmit Signals" of the Altera® Low Latency Ethernet 10G MAC User Guide (PDF), the tx_path_delay_10g_data and tx_path_delay_1g_data signal descriptions refer to a data width of 16/22 for the Arria® V and Stratix® V devices.

    tx_path_delay_10g_data tx_path_delay_1g_data signal signals should refer to a data width of 15/21.

    Resolution

    This problem has already been fixed in a new version of the Low Latency Ethernet 10G MAC User Guide (PDF).

    Related Products

    This article applies to 7 products

    Arria® V GZ FPGA
    Arria® V GT FPGA
    Arria® V GX FPGA
    Arria® V ST SoC FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA

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