Yes, there is an issue with the DPA Calibration Feature in the simulation models for Stratix® III and Stratix IV devices in Quartus® II software version 9.0 and all subsequent service packs.
You will find for an RTL simulation, the dpa_pll_cal_busy signal stays constantly high and the dpa_locked signal stays constantly low.
The correct behaviour is that dpa_pll_cal_busy is high during calibration and is low when the dpa is locked. This works for gate level simulation.
This issue will be fixed in a future version of Quartus II software.