Article ID: 000079868 Content Type: Error Messages Last Reviewed: 05/25/2023

Warning (332174): Ignored filter at <filename>.sdc: <hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco1ph[0] could not be matched with a pin

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see this warning in the Quartus® II software when compiling a design containing the the PLL Intel® FPGA IP in the Stratix® V, Arria® V, or Cyclone® V device families.
    The problem occurs when you manually apply a create_generated_clock constraint for your PLL instead of using the derive_pll_clocks constraint.

    The warning occurs due to PLL output counter name mismatches between the post-synthesis and post-fit netlists.

    Resolution

    To avoid this warning, perform one of the following two actions:

    • Use derive_pll_clocks to constrain your PLL.
    • Use wildcards in your create_generated_clock constraint as shown below:

    For an original constraint such as:

    create_generated_clock -name {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|divclk} /
    -source [get_pins {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco1ph[0]}]

    Replace the -source reference from vco1ph[0] to vco*ph[*]:

    create_generated_clock -name {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|divclk} /
    -source [get_pins {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco*ph[*]}] /

    This problem is fixed starting with the Intel® Quartus® Prime Pro or Standard Edition Software version 13.0.

    Related Products

    This article applies to 15 products

    Arria® V GX FPGA
    Stratix® V GS FPGA
    Cyclone® V GT FPGA
    Stratix® V GT FPGA
    Cyclone® V E FPGA
    Arria® V GZ FPGA
    Cyclone® V GX FPGA
    Arria® V GT FPGA
    Stratix® V E FPGA
    Stratix® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA