Article ID: 000080373 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why does the Intel® Stratix® 10 Avalon® -MM Interface for PCIe* IP with internal DMA send out the read mover "Done" status before it completes the data transfer?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This problem is due to a datapath race condition. The DMA read mover "Done" status update and the completion data are split internally into two (2) different paths/buffers. Data takes a longer path to the Avalon® -MM slave compared to the status update.

    Resolution

    This datapath race condition is easily observed in simulation. However, the read mover "Done" status reported a few clock cycles earlier than the data transfer completion will not be a problem in real hardware systems due to latency.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs