Critical Issue
Description
The documentation for the SoC HPS v.12.1 describes signals for the boot-from-FPGA feature. These signals are not accessible to logic in the FPGA portion of the SoC.
Resolution
Update to v14.0 or later of the following documents:
- The Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual (FPGA Manager and Instantiating the HPS Component chapters)
- The Arria V Device Handbook Volume 3: Hard Processor System Technical Reference Manual (FPGA Manager and Instantiating the HPS Component chapters)
- The Cyclone V SoC HPS Address Map and Register Definitions
- The Arria V SoC HPS Address Map and Register Definitions
These documents contain corrected descriptions of the f2h_boot_from_fpga_on_failure and f2h_boot_from_fpga_ready signals, indicating that the signals are always pulled high.