Article ID: 000081226 Content Type: Error Messages Last Reviewed: 06/07/2013

Warning: OUTCLK port on the PLL is not properly connected on <instance>. The output clock port on the PLL must be connected. Info: Must be connected

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When you compile the Triple Speed Ethernet (TSE) IP in LVDS mode for Arria® V devices, you will get the following warning messages during Analysis & Synthesis: 

 

Warning: OUTCLK port on the PLL is not properly connected on <instance>. The output clock port on the PLL must be connected.

    Info: Must be connected

Resolution

The reason for this warning is due to ALTLVDS_RX generating a slow PLL clock even though it is in soft-CDR mode and only the DPA clock is being used.

The warning simply indicates that the slow clock PLL has no fanouts.

 

Hence, this warning message can be safely ignored.

Related Products

This article applies to 2 products

Arria® V FPGAs and SoC FPGAs
Arria® V GX FPGA