Article ID: 000082189 Content Type: Troubleshooting Last Reviewed: 05/10/2023

Why do I get timing failures on the Intel® Arria® 10 Hard IP for PCI Express pld_clk_inuse_hip_sync signal?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software release 14.1, some constraints for the Intel® Arria® 10 Hard IP for PCI Express are missing.

    Paths to the signal pld_clk_inuse_hip_sync can be set as false paths.

    Resolution

    To work around this problem, add the following constraints to your top level constraint (.sdc) file after any derive_pll_clocks directives:

    # HIP testin pins SDC constraints
    set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
    set_false_path -from [get_pins -compatibility_mode *altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_rs_a10_hip:g_soft_reset.altpcie_rs_a10_hip|hiprst*]
    set_false_path -to  [get_registers *altpcie_a10_hip_pipen1b|pld_clk_inuse_hip_sync]
    set_false_path -from [get_pins -compatibility_mode *|*reset_status_sync_pldclk_r*]
    set_false_path -from [get_registers *altpcie_256_sriov_dma_avmm_hwtcl:apps|altpcierd_hip_rs:rs_hip|app_rstn]

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA