Article ID: 000084375 Content Type: Troubleshooting Last Reviewed: 12/14/2015

Why do I see a one clock cycle delay difference between RTL and gate level simulation?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® Prime software DSP register packing for V series devices, you may see a clock cycle delay difference on a register in gate level functional simulation compared to RTL functional simulation.
    Resolution

    To work around this problem either change fitter option "Auto Packed Registers" from "Auto" (default) to "Off" or download a patch for Quartus II software version 15.0.2

     

    This problem has been fixed beginning with version 15.1 Update 1 of the Quartus Prime software.

     

    Related Products

    This article applies to 15 products

    Cyclone® V E FPGA
    Stratix® V GS FPGA
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    Cyclone® V SX SoC FPGA
    Stratix® V GX FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V GT FPGA
    Arria® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA
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    Cyclone® V SE SoC FPGA

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