Article ID: 000084806 Content Type: Troubleshooting Last Reviewed: 06/28/2012

Possible Calibration Error for DDR2 and DDR3 Interfaces on Arria V, Cyclone V, and Stratix V Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects DDR2 and DDR3 products.

    Certain device and board skew combinations may experience calibration failure. During calibration failure, the EMIF Debug Toolkit may report the following error:

    Error: Read Calibration - No working DQSen phase found

    This error may indicate that the calibration routine has failed to complete DQS enable calibration.

    This issue may be more likely to occur with DDR3 interfaces operating at a frequency of 667 MHz or higher.

    Resolution

    The workaround for this issue is to download the device patch available here: http://www.altera.com/support/kdb/solutions/rd06202012_726.html.

    This issue will be fixed in a future version.

    Related Products

    This article applies to 3 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Stratix® V FPGAs