Article ID: 000085752 Content Type: Troubleshooting Last Reviewed: 04/06/2023

Why are the timing margins the same values for all corners when performing Report DDR in the Timing Analyzer for Intel® Arria® 10 FPGA external memory interfaces?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The I/O timing, which includes Address/Command, DQS gating, read capture, write and write levelling is fully calibrated over process, voltage, and temperature (PVT). Therefore, the margins are the same across all models. The Report DDR in the Timing Analyzer reports the worst case values over all corners for these calibrated interfaces.

Resolution

N/A

Related Products

This article applies to 3 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA