Article ID: 000085782 Content Type: Troubleshooting Last Reviewed: 08/07/2023

Why does my V-Series Avalon-MM DMA descriptor controller not use the new base address I programmed?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When you update the RC Read Status, Descriptor Base, RC Write Status, and Descriptor Base addresses, the descriptor controller will not use the new address(es) until all the descriptors specified in RD/WR_TABLE_SIZE have been exhausted.

     

    Resolution

    To change the Descriptor Base address, all the descriptors specified in RD/WR_TABLE_SIZE must have been exhausted, or the table size must be updated.

    Related Products

    This article applies to 14 products

    Cyclone® V SX SoC FPGA
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    Stratix® V GS FPGA
    Arria® V SX SoC FPGA
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    Arria® V ST SoC FPGA
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    Arria® V GX FPGA
    Arria® V GT FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA