Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1 with Intel® Stratix® 10 device, you might see the Shift Register (RAM Based) IP parameter editor error message mentioned above in the Platform Designer generation. This happened whenever you try to instantiate both the synchronous clear port and the clock enable port together.
To work around the problem, disable either the synchronous clear port or the clock enable port.
This restriction will be lifted starting with the Intel® Quartus® Prime Pro Edition Software version 18.0.