Article ID: 000085875 Content Type: Troubleshooting Last Reviewed: 06/06/2023

Why does the simulation of my Dual Port RAM Intel® FPGA IP have incorrect read-during-write behavior?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you might see incorrect old data behaviour for read-during-write operations when new data is expected.

    This problem only affects the simulation behaviour for Dual Port RAM Intel® FPGA IP with the following configuration for Intel® Stratix® 10 devices and Intel Agilex® devices :

    • RAM block type is MLAB
    • Read address is unregistered
    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel Agilex® 7 FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.