Article ID: 000086338 Content Type: Error Messages Last Reviewed: 06/21/2017

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/place_constraints.c, Line: 879

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Standard Edition software version 17.0 and earlier, you may see this internal error if your design contains Partial Reconfiguration regions and you violate the global promotion rules stated in Table 4-2 of the Design Planning for Partial Reconfiguration handbook chapter which can be accessed from the following link.

    /content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts-qps-handbook.pdf

     

    ... and you violate the global promotion rules given in the Supported Signal Types for Driving Clock Networks in a PR Region section of the Design Planning for Partial Reconfiguration chapter of the Quartus Prime Standard handbook.

    Resolution

    To avoid this error you must ensure you adhere to the global promotion rules stated in Table 4-2 of the Design Planning for Partial Reconfiguration handbook chapter

    This problem is scheduled to be resolved in a future release of the Quartus Prime Standard Edition software

    Related Products

    This article applies to 3 products

    Stratix® V FPGAs
    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs